用 TEXTIO 从外部激励文件驱动 VHDL 测试平台

从外部文件读取激励数据是控制 VHDL 中被测设备 (DUT) 的强大方式。通过在纯文本文件中编写信号值和仿真时间序列，设计者无需修改测试平台逻辑即可快速切换测试模式。本文是 VHDL 文件访问系列第二篇，演示如何用 TEXTIO 库读取激励文件并应用到 4 输入多路复用器。

测试用例概览

DUT 为标准异步 4 选 1 多路复用器，8 位数据字。测试平台不做输出验证——仅驱动输入以便手动观察波形。实体重现如下：

 entity mux_4 is port( din_0 : in unsigned(7 downto 0); din_1 : in unsigned(7 downto 0); din_2 : in unsigned(7 downto 0); din_3 : in unsigned(7 downto 0); sel : in unsigned(1 downto 0); dout : out unsigned(7 downto 0)); end entity; 

连接 DUT 的信号在测试平台架构中声明，标签 DUT 实例化：

 signal din_0 : unsigned(7 downto 0); signal din_1 : unsigned(7 downto 0); signal din_2 : unsigned(7 downto 0); signal din_3 : unsigned(7 downto 0); signal sel : unsigned(1 downto 0); signal dout : unsigned(7 downto 0); DUT: entity work.mux_4(rtl) port map ( din_0 => din_0, din_1 => din_1, din_2 => din_2, din_3 => din_3, sel => sel, dout => dout ); 

设计激励文件

虽多种格式可行，下例展示清晰、人类可读布局。每行代表一仿真步，含：

• wait_time – 相对上一步延迟（如 10 ns）
• sel – 2 位选择器值
• din_0 到 din_3 – 十六进制 8 位数据值
• 可选尾部注释以 # 开头，供控制台输出

行首注释被测试平台忽略；数据集后的注释打印到仿真器控制台。

 # Column description: # wait_time | sel | din_0 | din_1 | din_2 | din_3 # Optional console printout 0 ns 0 AA BB CC DD # Setting initial values 10 ns 1 AA BB CC DD # Testing by changing the selector signal 10 ns 2 AA BB CC DD 10 ns 3 AA BB CC DD 10 ns 3 A1 B1 C1 D1 # Testing by changing all data inputs 10 ns 3 A2 B2 C2 D2 10 ns 3 A3 B3 C3 D3 10 ns 3 00 00 00 D2 # Changing all unselected inputs 10 ns 3 01 02 03 D2 10 ns 3 11 22 33 D2 1 ns 0 CC DD EE FF # Changing all inputs fast 1 ns 1 DD EE FF CC 1 ns 2 EE FF CC DD 1 ns 3 FF CC DD EE 10 ns 0 00 00 00 00 # Simulation stop 

用 TEXTIO 读取文件

下面核心进程打开激励文件，解析每行，赋值给 DUT 输入，处理注释。假设文件格式良好——单空格分隔列，# 后跟单空格。

 PROC_SEQUENCER : process file text_file : text open read_mode is "stimulus.txt"; variable text_line : line; variable ok : boolean; variable char : character; variable wait_time : time; variable selector : sel'subtype; variable data : dout'subtype; begin while not endfile(text_file) loop readline(text_file, text_line); -- Skip empty lines and single‑line comments if text_line.all'length = 0 or text_line.all(1) = '#' then next; end if; read(text_line, wait_time, ok); assert ok report "Read 'wait_time' failed for line: " & text_line.all severity failure; hread(text_line, selector, ok); assert ok report "Read 'sel' failed for line: " & text_line.all severity failure; sel <= selector; hread(text_line, data, ok); assert ok report "Read 'din_0' failed for line: " & text_line.all severity failure; din_0 <= data; hread(text_line, data, ok); assert ok report "Read 'din_1' failed for line: " & text_line.all severity failure; din_1 <= data; hread(text_line, data, ok); assert ok report "Read 'din_2' failed for line: " & text_line.all severity failure; din_2 <= data; hread(text_line, data, ok); assert ok report "Read 'din_3' failed for line: " & text_line.all severity failure; din_3 <= data; wait for wait_time; -- Print trailing comment to console, if any read(text_line, char, ok); -- Skip expected newline read(text_line, char, ok); if char = '#' then read(text_line, char, ok); -- Skip expected newline report text_line.all; end if; end loop; finish; end process; 

仿真输出

ModelSim 运行时控制台显示尾部注释及累计仿真时间。下面摘录显示打印序列：

 # ** Note: Setting initial values # Time: 0 ns Iteration: 1 Instance: /file_stim_tb # ** Note: Testing by changing the selector signal # Time: 10 ns Iteration: 0 Instance: /file_stim_tb # ** Note: Testing by changing all data inputs # Time: 40 ns Iteration: 0 Instance: /file_stim_tb # ** Note: Changing all unselected inputs # Time: 70 ns Iteration: 0 Instance: /file_stim_tb # ** Note: Changing all inputs fast # Time: 91 ns Iteration: 0 Instance: /file_stim_tbf # ** Note: Simulation stop # Time: 104 ns Iteration: 0 Instance: /file_stim_tb # Break in Process PROC_SEQUENCER at file_stim_tb.vhd line 98 

测试平台产生的波形镜像文件中的时序和数据值，让设计者可视化验证 DUT 行为。

关键要点

• 外部激励文件给设计者细粒度测试序列控制，无需改测试平台代码。
• 用 TEXTIO 保持测试平台简洁，但要求严格文件格式。
• 始终包含自检机制——或对比行为模型，或在激励文件嵌入期望输出。

遵循上例，您可发挥 VHDL TEXTIO 全灵活性驱动复杂测试场景，同时保持测试平台结构清晰、可维护。