Verilog 运算符：综合必备的算术与控制运算符

无法处理的数据毫无用处，数字电路和计算机系统总需要某种计算。看看 Verilog 中哪些运算符能让综合工具实例化合适的硬件元件。

Verilog 算术运算符

若除法或取模运算符的第二个操作数为零，结果为 X。若幂运算符任一操作数为实数，结果也为实数。幂运算符第二个操作数为 0 时结果为 1 (a⁰)。

运算符	描述
a + b	a 加 b
a - b	a 减 b
a * b	a 乘 b
a / b	a 除以 b
a % b	a 模 b
a ** b	a 的 b 次幂

算术运算符使用示例：

module des;
reg [7:0] data1;
reg [7:0] data2;
initial begin
    data1 = 45; data2 = 9;
    $display ("Add + = %d", data1 + data2);
    $display ("Sub - = %d", data1 - data2);
    $display ("Mul * = %d", data1 * data2);
    $display ("Div / = %d", data1 / data2);
    $display ("Mod % = %d", data1 % data2);
    $display ("Pow ** = %d", data2 ** 2);
end
endmodule

仿真日志

ncsim> run
Add + = 54
Sub - = 36
Mul * = 149
Div / = 5
Mod % = 0
Pow ** = 81
ncsim: *W,RNQUIE: Simulation is complete.

Verilog 关系运算符

关系运算符表达式为真结果 1，为假结果 0。任一操作数为 X 或 Z 则结果为 X。关系运算符优先级低于算术运算符，所有关系运算符优先级相同。

运算符	描述
a < b	a 小于 b
a > b	a 大于 b
a <= b	a 小于等于 b
a >= b	a 大于等于 b

module des;
reg [7:0] data1;
reg [7:0] data2;
initial begin
    data1 = 45; data2 = 9;
    $display ("Result for data1 >= data2 : %0d", data1 >= data2);
    data1 = 45; data2 = 45;
    $display ("Result for data1 <= data2 : %0d", data1 <= data2);
    data1 = 9; data2 = 8;
    $display ("Result for data1 > data2 : %0d", data1 > data2);
    data1 = 22; data2 = 22;
    $display ("Result for data1 < data2 : %0d", data1 < data2);
end
endmodule

仿真日志

ncsim> run
Result for data1 >= data2 : 1
Result for data1 <= data2 : 1
Result for data1 > data2 : 1
Result for data1 < data2 : 0
ncsim: *W,RNQUIE: Simulation is complete.

Verilog 等价运算符

等价运算符优先级相同，低于关系运算符。结果为真则 1，为假则 0。逻辑等价 (==) 或逻辑不等价 (!=) 任一操作数为 X 或 Z 则结果为 X。可用情况等价 (===) 或情况不等价 (!==) 匹配包括 X 和 Z，结果总是已知值。

运算符	描述
a === b	a 等于 b，包含 x 和 z
a !== b	a 不等于 b，包含 x 和 z
a == b	a 等于 b，结果可未知
a != b	a 不等于 b，结果可未知

module des;
reg [7:0] data1;
reg [7:0] data2;
initial begin
    data1 = 45; data2 = 9;
    $display ("Result for data1(%0d) === data2(%0d) : %0d", data1, data2, data1 === data2);
    data1 = 'b101x; data2 = 'b1011;
    $display ("Result for data1(%0b) === data2(%0b) : %0d", data1, data2, data1 === data2);
    data1 = 'b101x; data2 = 'b101x;
    $display ("Result for data1(%0b) === data2(%0b) : %0d", data1, data2, data1 === data2);
    data1 = 'b101z; data2 = 'b1z00;
    $display ("Result for data1(%0b) !== data2(%0b) : %0d", data1, data2, data1 !== data2);
    data1 = 39; data2 = 39;
    $display ("Result for data1(%0d) == data2(%0d) : %0d", data1, data2, data1 == data2);
    data1 = 14; data2 = 14;
    $display ("Result for data1(%0d) != data2(%0d) : %0d", data1, data2, data1 != data2);
end
endmodule

仿真日志

ncsim> run
Result for data1(45) === data2(9) : 0
Result for data1(101x) === data2(1011) : 0
Result for data1(101x) === data2(101x) : 1
Result for data1(101z) !== data2(1z00) : 1
Result for data1(39) == data2(39) : 1
Result for data1(14) != data2(14) : 0
ncsim: *W,RNQUIE: Simulation is complete.

Verilog 逻辑运算符

逻辑与 (&&) 两操作数均为真或非零时结果为 1。逻辑或 (||) 任一操作数为真或非零时结果为 1。任一操作数为 X 则结果为 X。逻辑非 (!) 将非零/真操作数转为 0，零/假转为 1，X 保持 X。

运算符	描述
a && b	a 和 b 都为真时评估为真
a \|\| b	a 或 b 为真时评估为真
!a	非零转零，零转非零

module des;
reg [7:0] data1;
reg [7:0] data2;
initial begin
    data1 = 45; data2 = 9;
    $display ("Result of data1(%0d) && data2(%0d) : %0d", data1, data2, data1 && data2);
    data1 = 0; data2 = 4;
    $display ("Result of data1(%0d) && data2(%0d) : %0d", data1, data2, data1 && data2);
    data1 = 'dx; data2 = 3;
    $display ("Result of data1(%0d) && data2(%0d) : %0d", data1, data2, data1 && data2);
    data1 = 'b101z; data2 = 5;
    $display ("Result of data1(%0d) && data2(%0d) : %0d", data1, data2, data1 && data2);
    data1 = 45; data2 = 9;
    $display ("Result of data1(%0d) || data2(%0d) : %0d", data1, data2, data1 || data2);
    data1 = 0; data2 = 4;
    $display ("Result of data1(%0d) || data2(%0d) : %0d", data1, data2, data1 || data2);
    data1 = 'dx; data2 = 3;
    $display ("Result of data1(%0d) || data2(%0d) : %0d", data1, data2, data1 || data2);
    data1 = 'b101z; data2 = 5;
    $display ("Result of data1(%0d) || data2(%0d) : %0d", data1, data2, data1 || data2);
    data1 = 4;
    $display ("Result of !data1(%0d) : %0d", data1, !data1);
    data1 = 0;
    $display ("Result of !data1(%0d) : %0d", data1, !data1);
end
endmodule

仿真日志

ncsim> run
Result of data1(45) && data2(9) : 1
Result of data1(0) && data2(4) : 0
Result of data1(x) && data2(3) : x
Result of data1(Z) && data2(5) : 1
Result of data1(45) || data2(9) : 1
Result of data1(0) || data2(4) : 1
Result of data1(x) || data2(3) : 1
Result of data1(Z) || data2(5) : 1
Result of !data1(4) : 0
Result of !data1(0) : 1
ncsim: *W,RNQUIE: Simulation is complete.

Verilog 位运算符

该运算符将一操作数中的某位与另一操作数对应位结合计算单个位结果。

&	1	x	z
0	0	0	0
1	1	x	x
x	x	x	x
z	x	x	x

\|	0	1	x	z
0	0	1	x	x
1	1	1	1	1
x	x	1	x	x
z	x	1	x	x

module des;
reg data1 [4] ;
reg data2 [4] ;
int i, j;
initial begin
    data1[0] = 0; data2[0] = 0;
    data1[1] = 1; data2[1] = 1;
    data1[2] = 'x; data2[2] = 'x;
    data1[3] = 'z; data2[3] = 'z;
    for (i = 0; i < 4; i += 1) begin
        for (j = 0; j < 4; j += 1) begin
            $display ("data1(%0d) & data2(%0d) = %0d", data1[i], data2[j], data1[i] & data2[j]);
        end
    end
end
endmodule

仿真日志

ncsim> run
data1(0) & data2(0) = 0
data1(0) & data2(1) = 0
data1(0) & data2(x) = 0
data1(0) & data2(z) = 0
data1(1) & data2(0) = 0
data1(1) & data2(1) = 1
data1(1) & data2(x) = x
data1(1) & data2(z) = x
data1(x) & data2(0) = 0
data1(x) & data2(1) = x
data1(x) & data2(x) = x
data1(x) & data2(z) = x
data1(z) & data2(0) = 0
data1(z) & data2(1) = x
data1(z) & data2(x) = x
data1(z) & data2(z) = x
ncsim: *W,RNQUIE: Simulation is complete.

Verilog 移位运算符

两种移位运算符：

逻辑移位运算符 : << 和 >>
算术移位运算符 : <<< 和 >>>

module des;
reg [7:0] data;
int i;
initial begin
    data = 8'h1;
    $display ("Original data = 'd%0d or 'b%0b", data, data);
    for (i = 0; i < 8; i +=1 ) begin
        $display ("data << %0d = 'b%b", i, data << i);
    end
    data = 8'h80;
    $display ("Original data = 'd%0d or 'b%0b", data, data);
    for (i = 0; i < 8; i +=1 ) begin
        $display ("data >> %0d = 'b%b", i, data >> i);
    end
    data = 8'h1;
    $display (" data >> 1 = 'b%b", data >> 1);
end
endmodule

仿真日志

ncsim> run
Original data = 'd1 or 'b00000001
data << 0 = 'b00000001
data << 1 = 'b00000010
data << 2 = 'b00000100
data << 3 = 'b00001000
data << 4 = 'b00010000
data << 5 = 'b00100000
data << 6 = 'b01000000
data << 7 = 'b10000000
Original data = 'd128 or 'b10000000
data >> 0 = 'b10000000
data >> 1 = 'b01000000
data >> 2 = 'b00100000
data >> 3 = 'b00010000
data >> 4 = 'b00001000
data >> 5 = 'b00000100
data >> 6 = 'b00000010
data >> 7 = 'b00000001
data >> 1 = 'b00000000
ncsim: *W,RNQUIE: Simulation is complete.

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