Verilog 显示任务

显示系统任务主要用于显示信息和调试消息，以跟踪日志文件中的模拟流程，也有助于更快地调试。有不同组的显示任务和格式，它们可以打印值。

显示/写入任务

语法

$display 和 $write 按照参数在参数列表中出现的顺序显示参数。

  
  
$display(<list_of_arguments>);
$write(<list_of_arguments>);

  

$write 不附加换行符 到其字符串的末尾，而 $display 从下面的例子中可以看出。

示例

  
  
module tb;
  initial begin
    $display ("This ends with a new line ");
    $write ("This does not,");
    $write ("like this. To start new line, use newline char 
");
    $display ("This always start on a new line !");
  end
endmodule

  

ncsim> run
This ends with a new line 
This does not,like this. To start new line, use newline char 
Hi there !
ncsim: *W,RNQUIE: Simulation is complete.

Verilog 频闪灯

$strobe 在当前增量时间步结束时打印变量的最终值，并具有类似 $display 的格式 .

  
  
module tb;
  initial begin
    reg [7:0] a;
    reg [7:0] b;
    
    a = 8'h2D;
    b = 8'h2D;
    
    #10;                  // Wait till simulation reaches 10ns
    b <= a + 1;           // Assign a+1 value to b
    
    $display ("[$display] time=%0t a=0x%0h b=0x%0h", $time, a, b);
    $strobe  ("[$strobe]  time=%0t a=0x%0h b=0x%0h", $time, a, b);
    
    #1;
    $display ("[$display] time=%0t a=0x%0h b=0x%0h", $time, a, b);
    $strobe  ("[$strobe]  time=%0t a=0x%0h b=0x%0h", $time, a, b);
    
  end
endmodule

  

注意 $strobe 显示变量 b 的最终更新值 在时间 10ns，即 0x2E , 和 $display 仅在 11ns 的下一个模拟增量中拾取它。

ncsim> run
[$display] time=10 a=0x2d b=0x2d
[$strobe]  time=10 a=0x2d b=0x2e
[$display] time=11 a=0x2d b=0x2e
[$strobe]  time=11 a=0x2d b=0x2e
ncsim: *W,RNQUIE: Simulation is complete.
ncsim> exit

Verilog 连续监控器

$monitor 每当其参数列表中的变量或表达式发生更改时，有助于自动打印出变量或表达式值。实现了类似调用$display的效果 每次更新其参数后。

  
  
module tb;
  initial begin
    reg [7:0] a;
    reg [7:0] b;
    
    a = 8'h2D;
    b = 8'h2D;
        
    #10;                  // Wait till simulation reaches 10ns
    b <= a + 1;           // Assign a+1 value to b
    
    $monitor ("[$monitor] time=%0t a=0x%0h b=0x%0h", $time, a, b);
    
    #1 b <= 8'hA4;
    #5 b <= a - 8'h33;
    #10 b <= 8'h1;
  
  end
endmodule

  

注意 $monitor 就像一个在主线程后台运行的任务，它监视并显示其参数变量的值变化。新的 $monitor 任务在模拟过程中可以发出任意次数。

ncsim> run
[$monitor] time=10 a=0x2d b=0x2e
[$monitor] time=11 a=0x2d b=0xa4
[$monitor] time=16 a=0x2d b=0xfa
[$monitor] time=26 a=0x2d b=0x1
ncsim: *W,RNQUIE: Simulation is complete.

Verilog 格式说明符

为了在显示函数中打印变量，适当的格式说明符 必须为每个变量给出。

  
  
module tb;
  initial begin
    reg [7:0]  a;
    reg [39:0] str = "Hello";
    time       cur_time;
    real       float_pt;
    
    a = 8'h0E;
    float_pt = 3.142;
    
    $display ("a = %h", a);
    $display ("a = %d", a);
    $display ("a = %b", a);
    
    $display ("str = %s", str);
    #200 cur_time = $time;
    $display ("time = %t", cur_time);
    $display ("float_pt = %f", float_pt);
    $display ("float_pt = %e", float_pt);
  end
endmodule

  

ncsim> run
a = 0e
a =  14
a = 00001110
str = Hello
time =                  200
float_pt = 3.142000
float_pt = 3.142000e+00
ncsim: *W,RNQUIE: Simulation is complete.

Verilog 转义序列

有些字符被认为是特殊的，因为它们代表其他显示目的，例如换行符、制表符和换页符。为了打印这些特殊字符 , 每次出现这样的字符都必须转义 .

  
  
module tb;
  initial begin
    $write ("Newline character 
");
    $display ("Tab character 	stop");
    $display ("Escaping  " %%");
    
/*    
    // Compilation errors
    $display ("Without escaping ");       // ERROR : Unterminated string
    $display ("Without escaping "");       // ERROR : Unterminated string
*/
  end
endmodule

  

ncsim> run
Newline character 
 
Tab character	stop
Escaping  " %
ncsim: *W,RNQUIE: Simulation is complete.