数据转换器建模助力精准系统仿真
数据转换器建模助力精准系统仿真
工程师常面临紧张设计进度，几无时间回答数据转换器性能关键问题。本系列解答这些问题，始于探索如何为系统级仿真建模模数转换器 (ADC) 和数模转换器 (DAC)。
前作中作者考察 I/Q 组合应数字还是模拟实现，并概述稳健通信链路性能要求。本文在该基础上探讨如何量化和建模直采射频采样架构中 DAC 和 ADC 关键参数。
直采射频调制与解调
图 1 演示两种常见拓扑：直采射频 DAC 转换调制和直采射频 ADC 转换解调。DAC 和 ADC 统称数据转换器。
图 1(a). 调制器
图 1(b). 解调器
虽数据转换器非理想性链路级影响有充分文档，但此配置下 DAC 和 ADC 具体质量要求在文献中仍探索不足。
为何仿真数据转换器？
误码率 (BER) 研究需统计意义结果，典型要求数百至千错误事件。目标 BER 10⁻⁴ 需仿真 500 万比特数据。实现如此吞吐量需简洁而全面的转换器模型，捕获最有影响特征且无过大计算开销。
本文提出系统建模方法，分 ADC 为中心和 DAC 为中心两部分。注：Sigma-Delta 转换器本讨论排除。
模数转换器 (ADC) 模型
关键参考文献 ([4]–[18]) 覆盖高速 ADC 分析、建模、测试。特别是 [13]、[14]、[16]、[17] 等研究引入捕获非线性行为的高级模型。但许多工程师仍寻求更简单、更直观且忠实于真实性能的表示。
图 2 展示 5 位双极性 ADC 量化过程，有 32 个离散输出电平。峰值电压跨 +0.9375 V 至 –1.0 V，约 ±1 V。RF 工程师通常用均方根值；1 V 峰值正弦波均方根 0.707 V，相对满量程 –3 dB。为避免混淆，引入两单位：dBpeakFS 用于峰值-满量程比，dBrmsFS 用于均方根-满量程比。
图 2.
带宽选择是另一关键考量。传统音频 ADC 关注全奈奎斯特带宽，但直采射频采样仅需信号占用部分加保护带。定义“关注带宽”为将由数字信号处理器 (DSP) 处理的区域。图 3 形象化此概念。
图 3.
图中信号带宽和关注带宽宽度可能重合但中心频率不同，因带通采样中 ADC 时钟 (f_S) 作混频器本振。奈奎斯特频率 f_Nyquist = f_S/2。
选择模型开发输入信号
表征 ADC 需暴露其动态行为的测试信号。单音正弦波虽常见于数据手册，但零带宽、无幅度变化。双音输入（图 4）提供带宽和幅度调制，成硬件测试和仿真实用选择。许多厂商也提供双音激励性能数据。
图 4.
文献也提出其他信号形状——高斯频谱、AM、FM ([4], [12])。商业测试套件少见但专用应用有价值。
本系列下文将介绍基于有效位数 (ENOB) 的 ADC 模型。在此之前，读者可参考下方缩写、术语表和参考文献。
使用缩写
术语表
- Munson, Justin; "Understanding High Speed DAC Testing and Evaluation"; Analog Devices Application Note AN-928; 2013
- Arrants, Alex; Brannon, Brad; & Reeder, Rob; "Understanding High Speed ADC Testing and Evaluation"; Analog Devices Application Note AN-835; 2010
- Baker, Bonnie; "A Glossary of Analog‑to‑Digital Specifications and Performance Characteristics"; Texas Instruments Application Report SBAA147B; 2011
- Malobert, Franco; Data Converters; Springer Publishing; Chapters 2 and 9
- Myderrizi, I; Zeki, A; "Current‑Steering Digital‑to‑Analog Converters: Functional Specifications, Design Basics, and Behavioral Modeling"; IEEE Antennas and Propagation Magazine, vol.52, no.4, 2010
参考文献
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- [6] Kester, Walt; "The Good, the Bad, and the Ugly Aspects of ADC Input Noise—Is No Noise Good Noise?"; Analog Devices Tutorial MT‑004; 2008
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- [8] Kester, Walt; "Understand SINAD, ENOB, SNR, THD, THD+N, and SFDR"; Analog Devices MT‑003; 2008
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- [13] Traverso, P.A.; Mirri, D.; Pasini, G.; Filicori, F.; "A nonlinear dynamic S/H‑ADC device model based on a modified Volterra series"; IEEE Trans. Instrum. Meas.; 2003
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- [15] Kester, Walt; "ADC Noise Figure—An Often Misunderstood and Misinterpreted Specification"; Analog Devices MT‑006; 2014
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- [22] Myderrizi, I.; Zeki, A.; "Current‑Steering DACs: Functional Specifications, Design Basics, and Behavioral Modeling"; IEEE Antennas and Propagation Magazine; 2010
- [23] Lee, S.M.; Taleie, S.M.; Saripalli, G.R.; Seo, D.; "Clock‑Phase‑Noise‑Induced TX Leakage Estimation of a Baseband Wireless Transmitter DAC"; IEEE Trans. Circuits and Systems II; 2012
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- [25] Bae, K.; Shin, C.; Powers, E.J.; "Performance Analysis of OFDM Systems with Selected Mapping in the Presence of Nonlinearity"; IEEE Trans. Wireless Communications; 2013
- [26] Ling, W.A.; "Shaping Quantization Noise and Clipping Distortion in Direct‑Detection Discrete Multitone"; Lightwave Technology; 2014
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